Optimisation of full-custom logic cells using response surface methodology

Introduction: The design of digital circuits, especially for full-custom cells, is often a time consuming and laborious process relying on the intuition and heuristic knowledge of the designer. Optimising transistor sizes is the main key in meeting the various design specifications such as time-delay, area and power. The problem with this type of design optimisation is the large number of design variables leading to an explosion in the design space. Various solutions to these problems have been proposed which are based on the use of either static timing models [1], dynamic timing models [2] or a combination of the two [3]. Static timing models, while efficient in computation, do not take all transition states into account, resulting in low accuracy. Dynamic timing models, on the other hand, require the consideration of all possible input combinations and therefore suffer from the dimensionality problem. We propose to use a set of techniques known as design of experiments (DOE) [4] and response surface methods [5] to effectively deal with the optimisation problem while still being able to carry out the analysis using dynamic timing. The DOE techniques, particularly fractional factorial methods [4], can greatly reduce the number of combinations of design variables that need be tried (thereby ameliorating the dimensionality problem). For this given reduced set DOE, techniques greatly increase the information per simulation run [6]. Response surface models (RSMs) effectively replace the slow circuit-level simulator and allow instant calculation of the simulated responses.